A typical example of the output circuit is illustrated in FIG. 1. The output circuit 1 is provided in association with a memory cell array ( not shown ) arranged in rows and columns, and memory cells in each column are coupled to a pair of bit lines. Though not shown in the drawings, a column selector circuit is provided for select one of the bit line pairs, so that a complementary signal appears on a pair of data line 2 and 3 in accordance with a data bit read out from the memory cell accessed. A sense amplifier circuit 4 of the current mirror type is coupled to the data lines 2 and 3, and the sense amplifier circuit 4 comprises two series combinations of p-channel type field effect transistors 5 and 6 and n-channel type field effect transistors 7 and 8 coupled in parallel to a source of voltage level Vdd, and an n-channel type field effect transistor 9 coupled between the two series combinations and a ground terminal for activation of the sense amplifier circuit 4 in the presence of an activation signal SE. The sense amplifier circuit 4 thus arranged is operative to amplify the complementary signal on the data lines 2 and 3 in response to the activation signal SE for producing a data bit signal DB at an output node thereof 10.
The output circuit 1 further comprises a NOR gate 11, an inverter circuit 12 coupled in parallel to the output node 10 of the sense amplifier circuit 4, a NOR gate 13 coupled to the inverter circuit 12, and an output inverter circuit 14 driven by the NOR gates 11 and 13. The NOR gate 11 has a series combination of two p-channel type field effect transistors 15 and 16 and an n-channel type field effect transistor 17 coupled between the source of voltage level Vdd and the ground terminal and an n-channel type field effect transistor 18 coupled in parallel to the n-channel type field effect transistor 17, and the p-channel type field effect transistor 15 and the n-channel type field effect transistor 18 are provided for activation of a complementary inverter circuit formed by the p-channel type and n-channel type field effect transistors 16 and 17 in the presence of an output enable signal OE. The inverter circuit 12 is provided with a series combination of a p-channel type field effect transistor 19 and an n-channel type field effect transistor 20, and the NOR gate 13 is similar in circuit arrangement to the NOR gate 11. Namely, the NOR gate 13 has a series combination of two p-channel type field effect transistors 21 and 22 and an n-channel type field effect transistor 23 coupled between the source of voltage level Vdd and the ground terminal and an n-channel type field effect transistor 24 coupled in parallel to the n-channel type field effect transistor 23, and the p-channel type field effect transistor 21 and the n-channel type field effect transistor 24 are also provided for activation of a complementary inverter circuit formed by the p-channel type and n-channel type field effect transistors 22 and 23 in the presence of the output enable signal OE. The output inverter circuit 14 is provided with a series combination of an n-p-n type bipolar transistor 25 and an n-channel type field effect transistor 26 coupled between the source of voltage level Vdd and the ground terminal, and the n-p-n type bipolar transistor 25 and the n-channel type field effect transistor 26 are driven by the NOR gates 11 and 13, respectively. An output node is provided between the n-p-n type bipolar transistor 25 and the n-channel type field effect transistor 26 and coupled to a data output terminal 27.
Description is hereinunder made for read-out operations on the assumption that the memory cells respectively storing the logic "1" bit and the logic "0" bit are accessed in succession. At time t1 of FIG. 2, the complementary signal is supplied from the memory cell to the data lines 2 and 3 through the selector circuit, so that the data line 2 goes down to the low voltage level, but the data line 3 goes up to the high voltage level in accordance with the logic "1" bit stored in the memory cell. Since the data line 2 affects the logic level of the data bit signal DB, the data bit signal DB goes down to the low voltage level at time t2. With the output enable signal OE of the active low voltage level, the NOR gates 11 and 13 are activated to form the inverses at the output nodes thereof, respectively. However, the data bit signal DB is directly supplied to the NOR gate 11 but is supplied to the NOR gate 13 after inversion carried out by the inverter circuit 12. Then, the inverter circuit 12 and the NOR gate 11 simultaneously shift the output nodes thereof to the high voltage level at time t3, but the NOR gate 13 shifts the output node thereof to the low voltage level at time t4. However, the n-p-n type bipolar transistor 25 is activated by the NOR gate 11 at time t3, so that the data output terminal 27 is determined in voltage level around time t4.
Subsequently, the memory cell storing the logic "0" bit is accessed, and the complementary signal is supplied from the memory cell to the data lines 2 and 3 through the selector circuit, so that the data line 2 goes up to the high voltage level, but the data line 3 goes down to the low voltage level at time t5. At time t6, the data bit signal DB goes up to the low voltage level, and the NOR gates 11 and 13 are activated with the output enable signal OE of the active low voltage level. Then, the inverter circuit 12 and the NOR gate 11 simultaneously shift the output nodes thereof to the low voltage level at time t7, but the NOR gate 13 shifts the output node thereof to the high voltage level at time t8. Thus, the NOR gates 11 and 13 are completed the functions thereof at time t8, however, the output inverter circuit 14 needs to discharge the data output terminal 27 to shift the voltage level thereat. Then, the output terminal 27 is determined in voltage level at time t9.
A problem is encountered in the prior-art output circuit 1 in that a prolonged time period is consumed from the alternation of the complementary data signal on the data lines 2 and 3 to completion of the read-out operation. This is because of the fact that the inverter circuit 12 is provided between the sense amplifier circuit 4 and the NOR gate 13. In detail, if the memory cell storing the logic "1" bit is accessed, the delayed time period is approximately equal to the total sum of the respective time periods for amplifying the complementary data signal at the sense amplifier circuit 4, producing the inverse of the data bit signal DB at the NOR gate 11 and driving the data output terminal 27 by the output inverter circuit 14. However, the delayed time period is prolonged upon read-out operation from the memory cell storing the logic "0" bit due to the inverter circuit 12. Then, the semiconductor memory device should be adjusted to the longest time period consumed for the read-out operation regardless of the logic level of the data bit.